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1. #Deliver us the moon data recovery generator#
2. #Deliver us the moon data recovery serial#
3. #Deliver us the moon data recovery driver#

Kumar, “Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems,” 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 2018, pp. Hanumolu, “A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer,” 2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, pp. Hanumolu, “3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from −40☌ to 85☌ and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors,” 2020 IEEE International Solid- State Circuits Conference – (ISSCC), 2020, pp.

#Deliver us the moon data recovery driver#

Pal et al., “A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS,” 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. Hanumolu, “A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction,” 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. Park et al., “A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ☑40ppm inaccuracy from -40☌ to 95☌,” 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. Hanumolu, “A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,” in IEEE J. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,” in IEEE J. Hanumolu, “A VCO based highly digital temperature sensor with 0.034 ☌/mV supply sensitivity,” in IEEE J. Solid-State Circuits, vol.PP, no.99, pp.1-13

Hanumolu, “A 0.0021 mm² 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS,” in IEEE J. Hanumolu, “A fully-integrated low frequency input reference, 1-to-2048 cascaded digital frequency synthesizer using scrambling TDC,” IEEE Trans. Hanumolu, “A fully-integrated low frequency input reference, 1-to-2048 cascaded digital frequency synthesizer using scrambling TDC, ” IEEE Trans.

#Deliver us the moon data recovery serial#

Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver,” IEEE J. Hanumolu, “A 5GHz digital fractional-N PLL using a 1-bit delta-sigma frequency-to-digital converter in 65nm CMOS,” IEEE J. Hanumolu, “A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS,” in IEEE J. Hanumolu, “A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based Buck converter with seamless transition between PWM/PFM modes,” IEEE J. Hanumolu, “A 10-Gb/s/ch, 0.6-pJ/bit/mm power scalable rapid-ON/OFF transceiver for on-chip energy proportional interconnects,” in IEEE J. Hanumolu, “A 0.45-0.7V 1-6Gb/s 0.29-0.58pJ/b source-synchronous transceiver using near-threshold operation,” IEEE J.

#Deliver us the moon data recovery generator#

Hanumolu, “Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers,” IEEE J. Hanumolu, “A 6.75-to-8.25 GHz, 250fsrms-integrated-jitter 3.25 mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS,” IEEE J. Rylyakov, “34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers,” IEEE J. Hanumolu, “A 15-Gb/s Sub-Baud-Rate Digital CDR,” IEEE J. Hanumolu, “A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler,” IEEE J. Wang et al., “A 6 µW ±50 ppm/☌ ☑500 ppm/V 1.5 MHz RC Oscillator Using Self-Regulation,” IEEE Trans. Hanumolu, “A 0.016 mm 2 0.26- µW/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS,” IEEE J.

Megawer et al., “A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection,” IEEE J. Hanumolu, “A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques,” IEEE J. Hanumolu, “A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS,” IEEE J. Pilawa-Podgurski, “Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS,” IEEE J. Hanumolu, “A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling,” in IEEE Journal of Solid-State Circuits (Early Access).